Signal integrity (SI) grew out of the electromagnetic compatibility discipline in the early 1990s and gradually became a hot topic in its own right. Although the term SI never appeared in the title, one of the first books on the topic was Introduction to Electromagnetic Compatibility by Clayton Paul. About a decade later, power integrity (PI) became the new hot topic, creating a separate discipline on which a multitude of books and conference sessions were based.
SI was based on high-frequency RF and microwave knowledge, whereas PI tasks were handled primarily by AC/DC and DC/DC power supply designers, who preferred the low-frequency behavior of circuits. Although the basic rules and principles of physics apply to both SI and PI, the separate high-frequency and low-frequency considerations led to seemingly disconnected design rules.
Take, for instance, three-dimensional (3D) effects, which we usually associate with high-frequency SI problems, where the full-wave solution of Maxwell equations becomes necessary. They can happen when we analyze a right-angle turn in a PCB trace or look at the high-speed behavior of a plated through-hole. In SI, the full-wave effects become more noticeable at higher frequencies, where the physical dimensions are not negligibly smaller than the wavelength.
Still, it may be surprising to learn that in PI, 3D effects can equally show up at very low frequencies, sometimes in the kHz region and even at DC. These 3D effects are created by specific patterns and changes in the current density in conductors. As seen in Figure 1, the density of DC current at a sharp right-angle turn of a power strip will be very small at the outer point of the corner and could be very high at the inner corner.
We know that high-speed traces with a sharp bend will suffer from the capacitive loading at the outer “unused” portion of the turning trace. We see in Figure 1 that, at DC, the outer corner is equally “unused” and does not cause problems; it is just not necessary to have copper there. Instead, the problem at DC shows up on the opposite side of the power strip, at the inner corner, where the current density may exceed the safe limit.
Another example of complex 3D behavior at low frequencies was documented by measured and simulated data2, where the conductor geometry and the component placement interacted in a way that created a negative phase and negative slope of the magnitude of impedance. In Figure 2, the circuit in question is a small fixture consisting of two back-to-back SMA edge-mount coaxial connectors and four 10 milliohm surface-mount resistors.
With just metal pieces and resistors, we would expect an R-L-like impedance profile. But the frequency dependency in this case looks as if we had the series resonance of a low-Q bulk capacitor at around 1.5 MHz. However, there is no capacitor in this circuit—not one that could create that low of a series resonance. Instead, the reason for the impedance dip is the distributed nature of the resistance and inductance of the ground pegs of the SMA connectors, which interact with the multiple pieces of R-L parallel shunt elements created by the four resistors2.
3D effects at relatively low frequencies also show up in wafer-probe PDN measurements3. Figure 3s shows a computer rendering of two wafer probes measuring a chip’s core power supply across two adjacent power-ground via pairs in a 1-mm array. The inductive coupling between the two loops formed by the probe tips has to be removed from the measured data, either by de-embedding or by calibration. The coupling can be characterized on appropriate calibration substrates. The mutual inductance between the probe tip loops for three different probe tip geometries is shown in Figure 3b. Note that the mutual inductance has different frequency dependency at low frequencies for the three probe geometries.
Regardless of the frequency, 3D interactions among electrically small features noticeably impact PI simulations and measurements.
- “The Perils of Right-Angle Turns at DC,” by Istvan Novak, gEEk spEEk, May 14, 2020.
- “Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range,” by Istvan Novak et al., DesignCon 2010, Feb. 1–4, 2010, Santa Clara, California.
- “3D Connection Artifacts in PDN Measurements,” by Istvan Novak et al., DesignCon 2023, Jan. 30–Feb. 2, 2023, Santa Clara, California.
This column originally appeared in the May 2023 issue of Design007 Magazine.